Impact of On-chip Interconnect on In-memory Acceleration of Deep Neural Networks

With the widespread use of Deep Neural Networks (DNNs), machine learning algorithms have evolved in two diverse directions—one with ever-increasing connection density for better accuracy and other more compact sizing energy efficiency. The increase increases on-chip data movement, which makes efficient communication a critical function DNN accelerator. contribution this work is threefold. First, we illustrate that point-to-point (P2P)-based interconnect incapable handling high volume movement DNNs. Second, evaluate P2P network-on-chip (NoC) (with regular topology such as mesh) SRAM- ReRAM-based in-memory computing (IMC) architectures range This analysis shows necessity optimal choice an IMC Finally, perform experimental evaluation different DNNs to empirically obtain performance architecture both NoC-tree NoC-mesh. We conclude that, at tile level, appropriate employed edge, NoC-mesh necessary accelerate density. Furthermore, propose technique determine any given DNN. In technique, analytical models NoC end-to-end latency demonstrate optimization results up 6 × improvement energy-delay-area product VGG-19 inference compared state-of-the-art architectures.